As computer systems have advanced, processing power and speed have increased substantially. Processors operate by executing software comprising a series of instructions for manipulating data in the performance of useful tasks. The instructions and associated data are stored in a memory. Demands increasingly call for faster and faster memory access. Unfortunately, increasing the speed on the interface between the memory controllers and the memory is becoming increasingly difficult.
For example, current memory controllers and DRAM (dynamic random-access memory) use a wide parallel address bus to send address information from the memory controller to the DRAM. For low-speed interfaces like sDDR (system Double data rate) memory, the interfaces between the memory controller and the DRAM run at a slow enough frequency such that training and calibration is not required. However, the use of a parallel bus requires use of numerous pins on both the memory controller and memory which is expensive. For example, a system using 16 bit addresses will use 16 pins for the address. Thus by design, parallel links allow guaranteeing that what is sent is captured correctly on the other end.
A serial bus allows use of fewer pins. For example, with an eight to one serialization ratio, a 16 bit address can be sent over two pins. Serial buses send the data faster than parallel busses because the same amount of data is sent over fewer pins for a given time period. As the serial interface operates at a higher speed, it is difficult to satisfy the timing budget of both the memory controller and the memory. Thus, training is required to capture data sent over a serial link.
In some conventional serial memory interfaces, a complete serial-to-serial loopback is used. A complete serial-to-serial loopback requires the loopback link to be calibrated and operational a priori so as to not introduce error in the looped back address data. Thus, a serial-to-serial loopback requires the loopback and serial address bus to each be calibrated with a loopback link calibrated a priori. In other words, two busses need to be calibrated before the interface can be operational.
Thus, while serial buses may be more efficient in terms of pin efficiency, serial buses require training to calibrate sending of data over the serial link.